Cross domain electrostatic discharge (ESD) protection is becoming difficult to achieve in advanced semiconductor technology nodes due to a number of challenges, most commonly associated with the ever smaller size of devices such as transistors provided in an integrated circuit.
FIG. 1 shows an example of a conventional semiconductor device 10. The device has a digital domain that includes a digital domain power rail 2 and a digital domain ground rail 4 (these are also labelled DVDD and DVSS in FIG. 1, respectively). The device 10 also includes an analogue domain that has an analogue domain power rail 6 and an analogue domain ground rail 8 (these are also labelled AVDD and AVSS in FIG. 1, respectively). The digital domain and the analogue domain may form part of a mixed signal device.
The digital domain and the analogue domain are connected via a signal line 3 for passing signals between each domain. The digital domain includes a CMOS inverter having a PMOS transistor Mp1 and an NMOS transistor Mn1 for driving signals on the signal line 3 as is known in the art. Similarly, the analogue domain has an inverter that also comprises a pair of PMOS and NMOS transistors (Mp2 and Mn2) connected to the signal line 3 for receiving signals transmitted by the digital domain. Each CMOS inverter is connected between the power rail and ground rail of its respective domain.
As is well known in the art of ESD circuit protection, various different modes of ESD zapping are possible. Accordingly, the device of FIG. 1 is provided with a number of features to protect against ESD events. For instance, to protect against ESD zapping from the analogue domain ground rail 8 to the digital domain power rail 2, a local Charged Device Model (CDM) clamp is provided between the signal line 3 and the analogue domain ground rail 8. The local CDM clamp comprises a transistor that is labelled Mesd in FIG. 1, and provides a discharge path from the analogue domain ground rail 8 through Mesd, the signal line 3 and the transistor Mp1 to the digital domain power rail 2 in the event of such a zapping. This discharge path bypasses the transistors Mp2 and Mn2 of the CMOS inverter of the analogue domain, thereby to avoid damage to the gate oxide of either transistor during the ESD event.
In addition, a power rail clamp 14 is provided between the digital domain power rail 2 and the digital domain ground rail 4 as is known in the art. Similarly, a power rail clamp 16 is provided in the analogue domain between the analogue domain power rail 6 and the analogue domain ground rail 8. These power rail clamps 14 and 16 provide a discharge path for ESD currents flowing between the power rails and the ground rails of each respective domain. Accordingly, for instance, for ESD zapping between the digital domain power rail 2 and the digital domain ground rail 4, the power rail clamp 14 can provide a discharge path that bypasses the CMOS inverter including the transistors Mp1 and Mn1. Similarly, the power rail clamp 16 of the analogue domain can provide a discharge path for ESD zapping between the analogue domain power rail 6 and the analogue domain ground rail 8 that bypasses the analogue domain CMOS inverter and its transistors Mp2 and Mn2.
To provide a discharge path for ESD zapping to flow between the two ground rails, a pair of back-to-back diodes 12 are used to connect the two ground rails together, as is known in the art.
For cross domain zapping, a number of problems exist. For instance, for ESD zapping from the digital domain power rail 2 to the analogue domain ground rail 8, the ideal current path is through the ESD power rail clamp 14 and the pair of back-to-back diodes 12 as indicated by the dotted line 22 in FIG. 1. This discharge path avoids any of the delicate circuitry of the semiconductor device. In practice however, since the state of the gate nodes of the transistors Mp1 and Mn1 of the CMOS inverter of the digital domain is not generally known (for instance they may be floating), in some situations (the worst case being where the gate node is at zero volts at the time of the ESD event) at least some of the ESD current may follow an alternative discharge path. This alternative discharge path is indicated by the dotted line labelled 24 in FIG. 1. The alternative discharge path 24 flows through the transistor Mp1 of the CMOS inverter of the digital domain and along the signal line 3. In such situations, the transistor Mesd may form a path for the ESD current to reach the analogue domain ground rail 8. Absent this current path for the current to reach the analogue domain ground rail 8, a high voltage is applied by the ESD discharge to the gate oxide of the transistor Mn2 of the CMOS inverter of the analogue domain, which may potentially damage the gate oxide, causing failure of the semiconductor device.
It is anticipated that in many ESD events the discharge of the ESD current through Mesd would protect the gate oxide of Mn2. However, this is reliant upon Vav of Mesd being lower than the breakdown voltage of the gate oxide of Mn2 under positive ESD zapping from the digital domain power rail 2 to the analogue domain ground rail 8. However, for more advanced technology nodes in which the gate oxide of the transistor Mn2 is relatively thin (for example, less than 40 Angstroms), it is typically the case that the above-mentioned condition is not met, so that Mesd cannot turn on fast enough to protect the gate oxide of Mn2. Accordingly, in advanced technology nodes, it may be that the ESD protection provided for the semiconductor device 10, at least in the case of ESD zapping between the digital domain power rail 2 and the analogue domain ground rail 8 is insufficient to protect Mn2.
A known response to this problem is shown in FIG. 2. The semiconductor device 10 in FIG. 2 is similar to that described above in relation to FIG. 1. Only the differences between the two circuits will be described here.
In the example of FIG. 2, the signal line 3 is provided with an interface resistor 32 and also a discharge path is provided through a diode 34 from the signal line 3 to the analogue domain power rail 6.
Firstly, the interface resistor 32 causes a voltage drop on the signal line 3 that assists in ensuring that Vav of Mesd remains lower than the breakdown voltage of the oxide of Mn2 under ESD zapping from the digital domain power rail 2 to the analogue domain ground rail 8. Secondly, the diode 34 provides an alternative discharge path labelled by the dotted line 26 that avoids the CMOS inverter of the analogue domain. Thus, ESD current discharging through the signal line 3, can pass through the diode 34 to reach the analogue domain power rail 6, from where it may be discharged to the analogue domain ground rail 8 through the analogue domain power rail clamp 16.
However, the steps taken in FIG. 2 as described above themselves suffer from a number of deficiencies. Firstly, the provision of an interface resistor 32 on the signal line 3 is generally undesirable as this can adversely affect high frequency performance of the device 10. Secondly, the path through the diode 34 can lead to high leakage from the digital domain power rail 2 to the analogue domain power rail 6 if there is no clear usage of a power-up sequence.
U.S. Pat. No. 7,817,386 describes an ESD protection circuit for an integrated circuit with separated power domains. US2013/0279052 describes an ESD protection device with a tuneable holding voltage for a high voltage programming pad. Further examples of ESD protection are described in an article by Mototsugu Okushima entitled “ESD protection design for mixed-power domains in 90 nm CMOS with new efficient power clamp and GND current trigger (GCT) technique”, EOS/ESD Symposium 06-205, and in an article by Chen et al., entitled “Local CDM ESD Protection Circuits for Cross-Power Domains in 3D IC Applications”, IEEE transactions on device and materials reliability, Vol. 14, No. 2, June 2014.